Title | :: |
Provably Associating The Guilty Party To The Leakages |
Country | :: |
India |
Authors | :: |
Karthikeyan || mrs.V.Vimala |
Page | :: |
01-07 |
Intentional or unintentional escape of confidential information is beyond questionone in every ofthe foremost severe security threats that organizations face within the digital era. The threat currently extends to our personal lives: a excessof non-publicinfois out there to social networks and smartphone suppliers and is indirectly transferred to teflon third party and fourth party applications. During this work, we have a tendency togift a generic information lineage framework LIME for information flow across multiple entities that take two characteristic, principal roles (i.e., owner and consumer). We have a tendency tooutlinethe precise security guarantees needed by such an information lineage mechanism toward identification of a guilty entity, and determine the simplifying non-repudiation and honesty assumptions..........
Keywords: - ...
Title | :: |
Generating Unique Copies For Provable Multi- Copy Data Possession Scheme |
Country | :: |
india |
Authors | :: |
Sangavi. M ME-CSE PG STUDENT || V.Valarmathi || T.Sathya |
Page | :: |
08-10 |
Increasingly more and more organizations are opting for outsourcing data to remote cloud service providers (CSPs). Customers can rent the CSPs storage infrastructure to store and retrieve almost unlimited amount of data by paying fees metered in gigabyte/month. For an increased level of scalability, availability, and durability, some customers may want their data to be replicated on multiple servers across multiple data centers.
Title | :: |
Privacy-Enhancing Patient Profile Management |
Country | :: |
India |
Authors | :: |
sri Devi. R Me Cse || v.Vimala || t.Kujani |
Page | :: |
11-13 |
Collaborative healthcare environments offer potentialbenefits, including enhancing the healthcare quality deliveredto patients and reducing costs. As a direct consequence, sharing ofElectronic Health Records (EHRs) among healthcare providershas experienced a noteworthy growth in the last years, sinceit enables physicians to remotely monitor patients' health andenables individuals to manage their own health data more easily.However, these scenarios face significant challenges regardingsecurity and privacy of the extremely sensitive informationcontained in EHRs. Thus, a flexible, efficient and standardsbasedsolution is indispensable to guarantee selective identity informationdisclosure and preserve patient's privacy. We proposea privacyaware profile management approach that empowers thepatient role, enabling him to bring together various healthcareproviders as well as user-generated claims into an uniquecredential. User profiles are represented through an adaptiveMerkle Tree, for which we formalize the underlying mathematical model. Furthermore, performance of the proposed solution isempirically validated through simulation experiments.
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Data Access Control in Multi-owner Settings. In: Jajodia S., Zhou J. (eds) Security and Privacy in Communication Networks.
SecureComm 2010. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering,
vol 50. Springer, Berlin, Heidelberg
[2]. Yan-Cheng Chang and Michael Mitzenmacher. 2005. Privacy preserving keyword searches on remote encrypted data. In
Proceedings of the Third international conference on Applied Cryptography and Network Security (ACNS'05), John Ioannidis,
AngelosKeromytis, and Moti Yung (Eds.). Springer-Verlag, Berlin, Heidelberg, 442-455.
DOI=http://dx.doi.org/10.1007/11496137_30
[3]. Reza Curtmola, Juan Garay, Seny Kamara, and RafailOstrovsky. 2006. Searchable symmetric encryption: improved definitions and
efficient constructions. In Proceedings of the 13th ACM conference on Computer and communications security (CCS '06). ACM,
New York, NY, USA, 79-88. DOI=http://dx.doi.org/10.1145/1180405.1180417
[4]. Eu-Jin Goh. 2003. Secure Indexes. Cryptology ePrint Archive, Report: 216.
[5]. Lv Z., Hong C., Zhang M., Feng D. (2014) Expressive and Secure Searchable Encryption in the Public Key Setting. In: Chow
S.S.M., Camenisch J., Hui L.C.K., Yiu S.M. (eds) Information Security. ISC 2014. Lecture Notes in Computer Science, vol 8783.
Springer, Cham
ECE
Title | :: |
Hybrid Index Modeling Model for Memo System with Ml Sub Detector |
Country | :: |
India |
Authors | :: |
M. Dayanidhy || Dr. V. Jawahar Senthil Kumar |
Page | :: |
14-18 |
In recent times, we are able to transmit data in high rate with low complexity through Multiple-input multiple-output (MIMO) based spatial modulation(SM). Here, we reduce the MIMO diversity gain by tailoring with SM systems such that it is suitable for efficient low complexity system with tolerable diversity gain. Effects of the spatial modulation are balanced by introducing SM based MIMO systems with index modulation (IM) technique. Since diversity is reduced on transmitting side to balance the quality of service (QoS), we increase the accuracy in detectors by testing various detectors to achieve better performance. The efficiency of MIMO over high order constellations are verified through MATLAB BER simulation and complexity reduction is also proved to be an efficient one.
Keywords- MIMO, spatial modulation, index modulation, bit error rate, ML detector etc.
[1]. CHAO-WANG HUANG, PANG-AN TING, AND CHIA-CHI HUANG "A Novel Message Passing Based MIMO-OFDM Data
Detector with a Progressive Parallel ICI Canceller." IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL. 10,
NO. 4, APRIL 2011.
[2]. V. Tarokh, H. Jafarkhani, and A. R. Calderbank, "Space-time block codes from orthogonal designs," IEEE Trans. Inf. Theory, vol.
45, pp. 1456-1467, July 1999.
[3]. H. Jafarkhani, "A quasi-orthogonal space-time block code," IEEE Trans. Commun., vol 49, no. 1, pp. 1-4, Jan. 2001.
[4]. V. Tarokh, A. Naguib, N. Seshadri, and A. R. Calderbank, "Combined array processing and space-time coding," IEEE Trans. Inf.
Theory, vol. 45. pp. 1121-1128, May 1999.
[5]. A. F. Naguib, N. Seshadri, and A. R. Calderbank, "Applications of space-time block codes and interference suppression for high
capacity and high data rate wireless systems," in Proc. 32nd Asilomar Conf. Signals, Syst. Comput., pp. 1803-1810, 1998
Title | :: |
Hybrid throughput aware variable puncture rate coding for PHY-FEC in video processing |
Country | :: |
India |
Authors | :: |
S.Lakshmi || S.Selva Kumar Raja |
Page | :: |
19-21 |
It is attractive to be able to alter the coding rate, and hence the error correcting power, of a forward error correcting coder/decoder (codec) to provide a codec whose error correction capability can be matched to the requirements of the data communication system in which it is used. Punctured coding applied to convolutional encoding/Viterbi decoding offers a method of achieving this. And adoptive multi beam-forming alongside with MIMO diversity gain is used for considerable QOS enhancement in their Open Network Intermediate Data Rate system. This paper discusses the modification of a QoS constraint length 7, 1/2-rate codec to operate with punctured coding at rates up to 7/8. Following a brief discussion of the requirements for variable rate coding in communication systems the practical implementation of a prototype codec and considerations relating to performance characterization are discussed. Experimental results at various coding rates and MIMO are given, together with simulation of performance to demonstrate the sensitivity of performance to path history length at higher coding rates. It is concluded that the method is very suitable to provide variable coding rates and not suffers from increasingly severe practical limitations over high speed networks.
[1]. CHAO-WANG HUANG, PANG-AN TING, AND CHIA-CHI HUANG "A Novel Message Passing Based MIMO-OFDM Data
Detector with a Progressive Parallel ICI Canceller." IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL. 10, NO.
4, APRIL 2011.
[2]. V. Tarokh, H. Jafarkhani, and A. R. Calderbank, "Space-time block codes from orthogonal designs," IEEE Trans. Inf. Theory, vol. 45,
pp. 1456-1467, July 1999.
[3]. H. Jafarkhani, "A quasi-orthogonal space-time block code," IEEE Trans. Commun., vol 49, no. 1, pp. 1-4, Jan. 2001.
[4]. V. Tarokh, A. Naguib, N. Seshadri, and A. R. Calderbank, "Combined array processing and space-time coding," IEEE Trans. Inf.
Theory, vol. 45. pp. 1121-1128, May 1999.
Title | :: |
An Area Efficient High Throughput Color Demosaicking Scheme |
Country | :: |
India |
Authors | :: |
Meena Ezhil Arasi. M M.E || Mrs. B. Hemalatha, M.E. |
Page | :: |
22-24 |
A fully pipelined color demosaicking design to improve the quality of reconstructed images, a linear deviation compensation scheme was created to increase the correlation between the interpolated and neighboring pixels. Furthermore, immediately interpolated green color pixels are first to be used in hardware-oriented color demosaicking algorithms, which efficiently promoted the quality of the reconstructed image. A boundary detector and boundary mirror machine were added to improve the quality of pixels located in boundaries. In addition, a hardware sharing technique was used to reduce the hardware costs of three interpolators. The VLSI architecture in this work contains only 4.97 K gate counts and the core area is 60,229 um2 synthesized by using 0.18-um CMOS process. The operating frequency of this work is 200 MHz by consuming 4.76 mW. Compared with the previous lowcomplexity designs, this work has the benefits in terms of low cost, low power consumption, and high performance.
[1]. F. Cardells-Tormo and J. Arnabat-Benedicto, "Flexible hardware-friendly digital architecture for 2-D separable convolution-based
scaling," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 7, pp. 522–526, Jul. 2006.
[2]. P. Y. Chen, C. C. Huang, Y. H. Shiau, and Y. T. Chen, "A VLSI implementation of barrel distortion correction for wide-angle
camera images," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 1, pp. 51–55, Jan. 2009.
[3]. M. Fons, F. Fons, and E. Canto, "Fingerprint image processing acceleration through run-time reconfigurable hardware," IEEE
Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 12, pp. 991–995, Dec. 2010.
[4]. J. W. Han, J. H. Kim, S. H. Cheon, J.O.Kim, and S. J. Ko, "Anovel image interpolation method using the bilateral filter," IEEE
Trans. Consum. Electron., vol. 56, no. 1, pp. 175–181, Feb. 2010.
Title | :: |
On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation |
Country | :: |
India |
Authors | :: |
Mrs M.NANDHINI, M.E || Mr. J. SUDHAKAR., M.E., (Ph.D) |
Page | :: |
25-27 |
In the production of integrated circuits, testing is done to identify defective chips.An efficient LFSR polynomial computation to generate all possible test from test set & to achieve 100% fault coverage. To compute more efficient seed sets for highest randomization. Randomization of LFSR through seed changes and polynomial changes. The efficiency of randomized LFSR in transition reduction Leads to power reduction. In VLSI testing equipments generated input patterns are applied to CUT through scan cells in a serial manner (shift and scan method). The scan chain length is increased linearly with number of flip flops in CUT. In multiple scan chain scan cells will be grouped and test patterns will be applied to CUT in a parallel. In this scan design testing; all selected storage elements are replaced by scan cells.
[1]. Abu-Issa A and Quigley S. "Bit-swapping LFSR and scan-chainordering: A novel technique for peak- and average-power reduction
inscan-based BIST," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 2009 vol. 28, no. 5, pp. 755–759.
[2]. Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S and Roy K."Lowpower scan design using first-level supply gating," IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., 2005, vol. 13, pp. 384–395
[3]. Bonhomme Y, Girard P, Guiller L, Landrault C and Pravossoudovitch S. "A gated clock scheme for low power scan testing of logic
ICs or embedded cores," in Proc. 10th Asian Test Symp., 2001, pp.253–258.
[4]. Corno F, Rebaudengo M, Reorda M & Violante M. "A new BIST architecture for low power circuits," in Proc. Eur. Test Workshop,
1999, pp. 160–164.
Title | :: |
An Area Efficient Distributed Arithmetic Based DTT Using Approximated Circuit |
Country | :: |
India |
Authors | :: |
Sandhiya.S ME || Mr. P. Boopathy, M.E. |
Page | :: |
28-30 |
In recent years many works have been proposed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. All these work aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. But trigonometric functions are used and measure need to be taken to process this cosine values in digital systems. Here in this paper in order to reduce the number of arithmetic operations and replacing these trigonometric functions by polynomial based integer arithmetic DTT orthogonal transformation is proposed for low-complexity circuitry and low power consumption without compromising the quality. Here complex multipliers are replaced by shifter and adders for complexity reduction involved in matrix computations. Approximation error is less evenly distributed in non-trigonometric transform matrices. So here we introduce the approximate DTT with its associate fast algorithm to reduce the complexity. Finally hardware complexity and power reduction will be proved against DCT and its quality retention will also be proved through real time image processing applications.
Title | :: |
Low-Complexity Pipelined Architecture For Fbmc/Oqam Transmitter |
Country | :: |
India |
Authors | :: |
ms. C. Abinaya Pg In Vlsi || ms. S. Lakshmi., M.E., (Ph.D) |
Page | :: |
31-33 |
In this paper we propose cyclic prefix less Filter-Bank Multi-Carrier with Offset Quadrature Amplitude Modulation (FBMC/OQAM) system over OFDM for next generation wireless standards. We proved that overall throughput metrics of OFDM system in fact largely limits by delay insertion and also depends on many parameters and even with multistage pipelining data rate can't be extended up to 5G requirements. Therefore, the availability of efficient hardware implementations with maximum operating frequency becomes of high interest. In this work, pipelined hardware with maximized parallel processing architecture is used at the transmitter which capable of supporting several filter lengths with low complexity and its efficiency is compared with OFDM implementations. For a functional verification extensive test bench simulation is carry out and proposed architecture complexity analyzes in terms of multipliers used and memory resources with respect to a typical OFDM transmitter. Finally through hardware synthesis, its complexity gap and high throughput to OFDM is proved in implementation perspectives.
Title | :: |
Prefix Topology Basedhierarchical Bitwidthoptimization For Highperformance Fir Filter |
Country | :: |
India |
Authors | :: |
Ms. DELPHINE CHANDRA MARY D. M.E VLSI design || Ms. S. Lakshmi, M.E., (Ph.D.) |
Page | :: |
34-36 |
In we present prefixes topology based accumulation units w ith variable latency to link equations via parallel-prefix computation using various methodologies such as such as ripple carry adder, Kogge Stone adder, Brent Kung adder, Ladner Fischer adder and Han Carlson adder. This work is also permitted to design high-speed and unique MAC hardware structure using vedic multiplier, thereby making them suitable for any DSP applications. To prove the hardware efficiency of the Wallace tree multiplier unit it is compared with stateof- the-art methods like high speed vedic and shift and add based DA method. Moreover, this methodology has several attractive features such as simplicity, regularity and modularity of architecture. Also, the DA technique can be designed to meet low complexity demand requirements of FIR filter design, where the bit optimization is processed within the bounded delay..........
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